Semiconductor devices, including static and dynamic random access memories, microprocessors, logic devices, etc., commonly comprise polycrystalline silicon (poly) plugs or studs used as contacts. For example, poly plugs can be used to contact two levels of metal or as contacts for structures such as capacitors in dynamic random access memories (DRAMs).
To construct a structure comprising a poly plug, a conductive layer which the plug will contact is formed, then a first dielectric layer is deposited, masked, and etched to form a contact hole therein. A blanket poly layer is formed which fills the hole, then the poly layer is planarized such that poly is removed from horizontal surfaces but remains in the hole. Subsequently, a second dielectric layer is deposited and a mask is aligned such that an etch of the second dielectric layer will expose the poly plug. The second dielectric layer is often slightly over-etched to facilitate complete removal of the dielectric material from the contact to ensure the plug is exposed. A metal layer is formed by sputtering or chemical vapor deposition to fill the hole in the second dielectric layer and to contact the poly plug in the first dielectric layer.
With decreasing semiconductor device feature sizes it becomes increasingly difficult to accurately align the mask over the second dielectric layer with the poly plug so that the etched hole in the second dielectric layer strikes only the poly plug. Misaligning the mask results in the exposure and etching of the first dielectric layer during the etch of the second dielectric layer. Consequently, there is a high likelihood that a portion of the first dielectric material in the proximity of the plug will be etched, as this material is often similar to the material being etched above the plug. When a subsequent conductive layer is formed within the hole in the second dielectric layer, the material will fill the area around the plug. This can result in electrical shorting or altered electrical characteristics of the completed device.
An aluminum oxide etch stop layer has been proposed which reduces undesirable dielectric etches when forming contact holes to underlying layers. In such a process, a blanket aluminum layer is formed over the region to which contact is to be made and over a desirable dielectric layer such as a cap and a sidewall over a conductive line. The aluminum is oxidized, then a second dielectric layer is formed over the aluminum oxide and a patterned photoresist layer is formed over the second dielectric layer. The second dielectric layer is etched using the aluminum oxide as an etch stop. A second etch is performed which etches the aluminum oxide and stops on the first dielectric layer. This process, however, has the disadvantage that processes which etch aluminum oxide also etch poly. Thus, the aluminum oxide etch must be timed to prevent etching of the poly as the oxide is cleared from the plug. Timed etches lend themselves to under-etching, which can result in electrical opens, or to over-etching, which can result in shorting or forming structures with undesirable electrical properties.
A method for forming a structure such as the one above, or similar structures, which reduces or eliminates the stated problems would be desirable.